The present invention relates to integrated circuits and to methods for manufacturing them.
Conventional bulk CMOS (where the NMOS devices are formed in p-type areas of the substrate, and the PMOS devices are formed in n-type areas) does not scale very well. The circuit condition known as latchup (i.e. the firing of a parasitic thyristor between power and ground) must be avoided, and this means that a large minimum spacing from n+ to p+ source/drains--typically five times the minimum geometry or more--must be maintained by the circuit designer. This spacing rule means that a significant fraction of the total circuit area is consumed as mere empty space between NMOS and PMOS areas. As circuits are scaled to smaller dimensions, the p+ to n+ minimum spacing normally cannot be scaled as rapidly as the minimum geometry, and therefore an even larger fraction of total area is wasted on the n+ to p+ spacing.
To avoid this constraint and also provide increased immunity to single event upset, various SOI (silicon-on-insulator) devices have been proposed. If the NMOS and PMOS devices are not part of the same semiconductor body, then latchup cannot happen, and n+ to p+ spacing ceases to be a relevant constraint.
However, many such proposed structures have turned out to have substantially lower performance than bulk CMOS, and have also turned out to be very difficult to fabricate. The lower performance commonly results from the use of polysilicon or annealed polysilicon for one of the device types, usually the PMOS device. The difficulties in fabrication are exacerbated by attempts to make a stacked CMOS structure--i.e. one in which the PMOS device lies over the gate to the NMOS device, so that the same line which is the front side gate for the NMOS device is the backside gate for the PMOS device--although it has been widely recognized that such structures would be highly advantageous for their compactness. One example of such a proposed structure is shown in U.S. Pat. No. 4,502,202 to Malhi.
The present invention provides a different way to build CMOS structures which are extremely compact, free of latchup and associated design constraints, relatively immune to single event upset, provide high channel mobility, and are not excessively difficult to fabricate.
In the present invention, CMOS logic is configured by placing the NMOS and PMOS devices on facing walls of a trench, with an insulated gate in between them to control both.
Another advantage of the present invention is that logic built according to the present invention is extremely easy to design, since the necessity for an n+ to p+ design rule is totally removed. Since design time is a major factor in modern integrated circuit costs, this is an important advantage.
Published work has described a vertical IGFET on the sidewall of a trench. See Richardson et al., A Trench Transistor DRAM Cell (paper 29.6 at the 1985 IEDM), which is hereby incorporated by reference. However, such vertical devices are not well suited for random logic, because the bottom node is not easily accessible. Thus such a transistor would be well suited for the pass transistor of a one transistor DRAM cell, but would be less easily adaptable to provide a pass gate in an SRAM cell.
Thus, it is an advantage of the present invention that a highly compact transistor-in-trench structure is provided, wherein the bottom node is readily accessible.
Moreover, the best prior transistor-in-trench structures have normally had the channels of the transistors in bulk material, so that p+ to n+ spacings would still be a potential problem if such structures were sought to be adapted to CMOS.
Thus, it is a further advantage of the present invention that a highly compact transistor-in-trench structure is provided, wherein full CMOS circuits can be implemented without n+ to p+ spacing problems.
In some embodiments of the invention, some recesses can be configured to contain only NMOS devices while other nearby trenches are configured to contain only PMOS devices. This loosens the alignment constraints of fabricating both NMOS and PMOS devices in a common trench, and still retains some of the advantages of the invention for close-packing of CMOS circuits.
In some embodiments of the invention, a self-aligned etch is used to bring a metal pillar contact to the output node of a CMOS inverter up through the middle of a trench, so that contact from metallization to the active device is simplified. Such embodiments have the further advantage, in addition to others mentioned, that extremely compact layout is permitted.
In some embodiments of the invention, the inverter is fully oxide isolated, with no contacts to substrate whatsoever. Such embodiments have the further advantage, in addition to others mentioned, that single-event upset is very much reduced.
In some embodiments of the invention, the power and ground lines are routed through buried diffusions, but all nodes to which discretionary wiring is necessary are brought out to surface areas. Such embodiments have the further advantage, in addition to others mentioned, that contact etching and constraints are simplified, and the design rules relating to placement of contacts can in general be simplified.
In some embodiments of the invention, the etch which forms the input gate is prolonged to etch into the substrate, and oxide refill of this etch then provides improved isolation between power and ground diffusions in the substrate.
In some embodiments of the present invention, the n+ and p+ polysilicon layers which provide the top source/drain contacts for the NMOS and PMOS devices are elongated past the active area of the devices, so that a surface contact can be made to these polysilicon lines to provide the output.
In the presently preferred process embodiment of the invention, after patterned implantations have formed the bottom n+ and p+ regions, a selective epitaxy step is used to grow upward (into an opening in field oxide) the nearly intrinsic silicon which will provide the channel regions for the active devices. A patterned implant is then used to dope the channel regions appropriately. (Optionally, if this epitaxial material is deposited using appropriate in-situ doping, only one side may need a patterned implant to set its conductivity type.)
After this has been done, a top polysilicon layer is deposited and heavily doped using a patterned implantation (either with one or with two masking steps), to form n+ and p+ polysilicon regions which will provide the top source/drain contact areas for the NMOS and PMOS devices. (Outdiffusion from this heavily doped polysilicon film will actually form shallow junctions within the crystalline regrown semiconductor, which will function as the actual source/drain regions.)
Another patterned etch is then used to cut a slot across the epitaxial material within at least some of the openings, so that an insulating dielectric can be formed on the sidewalls of this slot and the gate electrode placed therein.
In some embodiments, a self-aligned sequence is then used to define a smaller hole within this slot, so that an insulated metal post can reach down and make contact with the bottom n+ and p+ diffusions. However, this class of embodiments has the disadvantage that the parasitic capacitance of the input to the output nodes may be rather large.
In embodiments where the bottom n+ and p+ regions are not oxide isolated, one of them is preferably junction isolated. For example, where the substrate is p-type, the p+ bottom region is preferably shallower than the n+ bottom regions, so that the p+ bottom region is junction isolated from the substrate.
In another class of embodiments, solid phase epitaxy is used to define crystalline semiconductor on oxide regions for the bottom n+ and p+ regions.
Since the input gate is itself preferably conformally deposited polysilicon, this input gate may be routed across the chip to perform other circuit functions as well.
Since the conductivity types of the polysilicon channels are determined by implantation, it is not strictly necessary for every trench to have a PMOS device on one side and an NMOS device on the other. (This configuration provides a single inverter gate, but of course many other logic gate configurations are desirable.) Some trenches may include two PMOS devices, some trenches may include two NMOS devices, some trenches may include only one active device, or (with the addition of some additional steps (e.g. a second slot etch) to provide isolation along the trench walls) more than two active devices may be included in a single trench.
In some embodiments of the present invention, the bottom n+ and the bottom p+ nodes do not have to be connected together. This provides substantial additional flexibility in configuring random logic.
According to the present invention there is provided: A method for fabricating integrated circuits, comprising the steps of: providing a substrate including at least one monocrystalline semiconducting portion near a surface thereof; introducing dopants at high concentration into predetermined surface areas of said semiconducting portion of said substrate; providing a growth-blocking material over said semiconducting portion of said substrate, said growth-blocking material including openings to expose said semiconducting portion of said substrate at predetermined locations; selectively epitaxially growing additional semiconductor material on said substrate, under conditions such that said additional semiconductor material grows epitaxially on exposed areas of said monocrystalline semiconducting portion of said substrate and does not grow at all on said growth-blocking material; introducing dopants into said selectively epitaxially grown material in areas such that in at least some of said openings in said growth-blocking material said selectively epitaxially grown material includes both n-type portions and p-type portions; etching away portions of said selectively epitaxially grown material in at least some of said openings to separate n-type portions thereof from p-type portions thereof; forming a thin film insulated control gate layer having portions extending into at least one said recess and capacitively coupled to both said n-type portion and p-type portion of said selectively epitaxially grown material.
According to the present invention there is also provided: An integrated circuit device comprising: a thick dielectric having at least one recess therein; an n-type insulated gate vertical field effect transistor on one side of said recess; a p-type insulated gate vertical field effect transistor on another side of said recess separate from said n-type vertical field effect transistor; and a control gate in said recess connected to control current flow both in said n-type and in said p-type field effect transistors.
According to the present invention there is also provided: An integrated circuit device comprising: a thick dielectric having at least one recess therein; an trench running across said recess from one side to an opposite side; a body of n-type semiconducting material on a third side of said recess, and a body of p-type semiconducting material on a fourth side of said recess, said n-type body being laterally separated from said p-type body within said recess by said trench; a control gate located in said recess and insulated from and capacitively coupled to a surface of said n-type body and also a surface of said p-type body, whereby voltages applied to said control gate control surface carrier densities at respective surfaces of said respective bodies.